1. Field of the Invention
The present invention generally relates to a wafer-level package, a method of manufacturing thereof, and a method of manufacturing semiconductor devices from such a wafer-level package. The present invention particularly relates to an improved wafer-level package to be tested by a preliminary test (PT) and a final test (FT), a method of manufacturing the wafer-level package, and a method of manufacturing semiconductor devices using such a wafer-level package.
Recently, there is a need for more efficient manufacturing and testing processes of semiconductor devices. In order to achieve this, a full test (including PT and FT) is implemented on an uncut semiconductor wafer before being cut into individual semiconductor devices. As will be described below, the full test has several advantages over the related art in which the semiconductor wafer is cut into individual semiconductor devices and each of the semiconductor devices are tested individually.
The advantages include good handling efficiency, a possibility of sharing certain equipment and reduced space. If the wafer sizes are equal, handling equipment can be shared. Also, it is possible to save space otherwise taken up as a storage area and/or an installation area when accommodating individualized semiconductor devices (LSI chips) in containers such as a tray.
For higher density mounting, there is an increasing need for a KGD (Known-Good Die) and a real-chip-size package (a package having the same size as that of the semiconductor chip). However, with the package structure of the semiconductor device of the related art, which does not correspond to the KGD or the real-chip-size package, the area of the package is greater than that of the semiconductor chip. Therefore, the semiconductor wafer must be individualized at some point before packaging. Thus, with the package structure of the related art, the entire process, that is to say, from a manufacture process to a test process, cannot be implemented on the semiconductor wafer.
However, with the KGD or the real-chip-size package, since the final package configuration corresponds to the area of the semiconductor chip, the entire process can be implemented on the semiconductor wafer. Therefore, the above-described advantages can be obtained.
2. Description of the Related Art
Recently, there is an increasing interest in a wafer-level package which is a package structure with which the entire process from the manufacturing process to the testing process can be implemented on a semiconductor wafer. The wafer-level package includes a semiconductor wafer provided with a plurality of semiconductor chip circuits with chip terminals, external connection terminals, redistribution traces connecting the chip terminals and the external connection terminals, and an insulating material such as a sealing resin. The insulating material is provided for protecting the semiconductor chip circuits and the redistribution traces. A structure without the insulating material is also possible.
The wafer-level package may be used in two different configurations. One is in the form of a wafer (i.e., before being cut) and the other is in form of individual semiconductor devices (i.e., after cutting into individual semiconductor chip circuits.)
In the following, the wafer-level package of the above-described structure will be described with regard to a test process thereof. With the wafer-level package, like that of the semiconductor devices of other configurations, the manufacture process includes a test process. The test process generally includes a preliminary test (PT) and a final test (FT).
The PT is a test implemented before providing the insulating material. The PT is a general test such as a conduction test of the interconnections, and thus does not include the operation test of the semiconductor chip circuit itself. Since the PT is implemented before providing the insulating material, the PT can be implemented using the chip terminals provided on the semiconductor chip circuit.
The PT is particularly advantageous for the package structure of the semiconductor devices of the related art (hereinafter, referred to as a conventional package), which are not designed for the KGD or for the real-chip-size package. In a manufacture process of the conventional package, the PT is followed by a cutting process (i.e., dicing process) for individualizing the semiconductor wafer into the semiconductor devices. Then, only those semiconductor devices, which were determined good in the PT, are provided with the insulating material and undergo the FT. In other words, those semiconductor devices, which were determined bad in the PT, are not provided with the insulating material and also do not undergo the FT. Thus, the manufacture efficiency can be improved.
The FT is implemented after providing the insulating material. The FT is a total test including the operation test of the semiconductor chip circuit. Since the FT is implemented after the insulating material has been provided, the FT can only be implemented using the external connection terminals exposed from the insulating material. In other words, the terminals (such as the chip terminals) other than those generally used by the users are not exposed. Therefore, the chip terminals sealed in the insulating material cannot be used in the FT.
Therefore, in the related art, the wafer level package is tested by, first, implementing the PT before providing the insulating material using the chip terminals which are not yet covered with the insulating material. After the PT, the insulating material is provided, and then the FT is implemented using the external connection terminals exposed from the insulating material.
In the test process of the related art, the object of implementing the PT is to improve manufacture efficiency by avoiding the insulating material being provided on bad semiconductor devices and thus avoiding the FT being implemented thereon. On the contrary, with the wafer-level package, all semiconductor chip circuits, including circuits of the bad semiconductor devices, are provided with the insulating material and undergo the FT, so that it is not necessary to implement the PT before the FT.
Also, as has been described above, the wafer-level package is used for simplifying the manufacture process by using the semiconductor wafer from the manufacture process to the test process. For further simplifying the manufacture process, the PT and the FT, which in the related art were implemented as two separate tests, can be integrated into a single test process.
When the PT and the FT are integrated into a single test process, the integrated test process can be carried out either before providing the insulating material (i.e., when the PT is implemented in the related art) or after providing the insulating material (i.e., when the FT is implemented in the related art). When the integrated test process is implemented before providing the insulating material, it is not possible to detect any failure produced in the semiconductor chip circuit while providing the insulating material. Thus, the test process should be implemented in a later step in the manufacture process of the semiconductor device.
On the contrary, when the integrated test process is implemented after providing the insulating material, only the external connection terminals exposed from the insulating material may be connected to test equipment (e.g., a semiconductor tester). That is to say, the chip terminals include terminals which do not serve as the external connection terminals, but can be used for testing the semiconductor chip circuit (hereinafter referred to as test chip terminals). There is a drawback that the test chip terminals will be covered with the insulating material, so that the test using the test chip terminals cannot be implemented after providing the insulating material.
In order to avoid such a drawback, test terminals may be provided in a region of the semiconductor chip circuit region, which terminals are exposed from the insulating material and are connected to the above-described test chip terminals. Thus, with such test terminals, all tests including the PT and the FT (full test) can be implemented after providing the insulating material.
However, the test terminals will not be used after the test process, and thus become unwanted terminals for the package. Such test terminals provided on the semiconductor chip circuit forming region results in an increase in the size of the semiconductor chip circuit forming region due to an area occupied by the test terminals. Accordingly, it is not possible meet the requirement for a miniaturization of the semiconductor device.
Also, when the test terminals are provided at a position adjacent to the external connection terminals used for operating the semiconductor chip, the test terminals may also be mistakenly mounted on a mounting board. In such a case, a false operation may occur. Therefore, the test terminals should not remain on the package after the insulating material has been provided.
Further, the PT can be omitted (that is to say, all tests can be implemented in the FT), but as has been described above, not all test chip terminals can be used in the FT. Therefore, tests, which used to be implemented in the PT only, cannot be implemented. For example, if the RAM and logic circuits are mounted in a mixed manner, a single test of the RAM cannot be carried out. At the same time, recently, since a high reliability is required for the semiconductor device, the PT cannot be omitted just for the sake of simplifying the manufacturing process.
From the above-described reasons, the PT and the FT have not been integrated in the related art. First, the PT is implemented, and then the insulating material is provided. Finally, the FT is implemented. Therefore, there is a problem that the manufacture process of the wafer-level package is complicated and thus the manufacture efficiency is decreased and the manufacture cost is increased.
Accordingly, it is a general object of the present invention to provide a wafer-level package, a method of manufacturing thereof, and a method of manufacturing a semiconductor device from such a wafer-level package which can solve the problems described above.
It is another and more specific object of the present invention to provide a wafer-level package, a method of manufacturing thereof, and a method of manufacturing a semiconductor device from such a wafer-level package which can improve a manufacturing efficiency and reduce a manufacturing cost.
In order to achieve the above objects according to the present invention, a wafer-level package includes:
a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, the chip terminals including at least one test chip terminal and at least one non-test chip terminal;
at least one external connection terminal electrically connected to the at least one non-test chip terminal;
at least one redistribution trace provided on the semiconductor wafer, a first end of the redistribution trace being connected to one of the test chip terminals and a second end of the redistribution trace being extended out to a position offset from the one of the chip terminals;
at least one testing member provided in an outer region of the semiconductor chip circuit forming region, the second end of the redistribution trace being connected to the least one testing member; and
an insulating material covering at least the redistribution trace, the at least one external connection terminal and the at least one testing member being exposed from the insulating material.
With the wafer-level package described above, even when the testing member is provided, the semiconductor chip circuit forming region will not become large. Therefore, the size of each individualized semiconductor device will be small compared to that of the structure in which the testing member is provided in the semiconductor chip circuit forming region.
Also, the testing member is provided in the outer region of the semiconductor chip circuit forming region, which outer region is to be removed upon individualizing into semiconductor devices. Therefore, even if the testing member is provided on the wafer-level package, the operating condition of the individualized semiconductor device will not be altered.
In order to achieve the above object, a wafer-level semiconductor device is disclosed, which includes:
a semiconductor wafer having chip circuit forming regions;
at least one testing member provided in an outer region of the chip circuit forming regions; and
a line provided on the semiconductor wafer and connecting the at least one testing member and a test terminal provided in one of the chip circuit forming regions.
It is still another object of the present invention to provide an easier method of manufacturing the above-described wafer-level package.
In order to achieve the above object, a method of manufacturing a wafer-level package includes the steps of:
a) preparing a semiconductor wafer having at least one semiconductor chip circuit forming region each provided with a semiconductor chip circuit and a plurality of chip terminals, at least one of the chip terminals being a test chip terminal and at least one being a non-test chip terminal;
b) providing a redistribution layer including an insulating film having through holes on the semiconductor wafer and an electrically conductive film formed on the insulating film, the film being formed into redistribution traces having a predetermined pattern;
c) providing external connection terminals and at least one testing member on the redistribution layer, the at least one testing member being provided at an outer region of the at least one semiconductor chip circuit forming region and connected to the test chip terminal via at least one of the redistribution traces;
d) testing the at least one semiconductor chip circuit using the at least one testing member; and
e) providing a sealing resin on the redistribution layer in such a manner that top parts of the external connection terminals and the at least one testing member are exposed from the sealing resin.
With the above-described method, the external connection terminals and the testing members can be provided simultaneously. Further, the PT and the FT can be implemented simultaneously. Thus, the package manufacturing process and the test process can be simplified.
It is yet another object of the present invention to provide an easier method of manufacturing at least one semiconductor device using the above-described wafer-level package.
In order to achieve the above-described object, a semiconductor device manufacturing method includes the steps of:
a) manufacturing the wafer-level package as described above,
b) testing the at least one semiconductor chip circuit provided in the at least one semiconductor chip circuit forming region by means of said at least one testing member; and
c) after the step b), cutting the wafer-level package along the outer region so as to manufacture at least one individualized semiconductor devices.
With the above-described method, external connection terminals and the testing member can be provided simultaneously. Further, the PT and the FT can be implemented simultaneously. Thus, the package manufacturing process and the test process can be simplified.
Also, the testing member will be removed when individualizing the semiconductor devices, so that the operating condition of the individualized semiconductor device will not be altered.
It is yet another object of the present invention to provide a semiconductor device which can be manufactured according to a method of the present invention.
In order to achieve the above object, a semiconductor device includes:
a semiconductor chip;
a test terminal and a non-test terminal provided to the semiconductor chip; and
a line which is connected to the test terminal and extends out of a circuit forming region.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.